Talk:List of HDL simulators

Current list is incomplete

Focus is primarily Verilog/SystemVerilog and VHDL simulators. Missing is SystemC and many other HDL language simulators.

Do any other "languages" actually belong here? Such as Mast or analog mixed signal variants of the simulators that actually appear in this list?

RickEversole (talk) 16:41, 19 February 2020 (UTC)

Does this really need to be its own article?

Does this really need to be its own article? This seems to duplicate some effort in the Verilog page. If it does make sense to make this a page of its own, perhaps the Verilog article should be coordinated with this by adding a link here.

Steveicarus 03:06, 18 May 2007 (UTC)

Yes it needs to be it's own article but needs extensive edits to clear up talk issues. It definitely needs to cross link to the various languages that are mentioned.

This is not just a list of simulators for a single language and since the major commercial simulators from [[Cadence_Design]Cadence Design Systems], [[Mentor_Graphics]Mentor], and [[Synopsys]Synopsys]support Verilog/SystemVerilog, VHDL and SystemC, it makes sense to have a single list that has lists for all three HDLs (I lump Verilog and SystemVerilog together as one as SystemVerilog replaces "Verilog" as a standard) RickEversole (talk) 15:23, 19 February 2020 (UTC)

Full disclosure

It turns out that the author of this article, ngsayjoe, is affiliated with the zeemz tool listed here, so I guess that it is not accident that it is the "most user friendly and affordable" tool on the list. This person has also appeared comp.lang.verilog performing similar stealth marketing.

My independence may also be suspect because I'm the author of Icarus Verilog, which is also on this list. I'll remove the "most popular" for that entry because whether it is true or not (I have opinions that I'll keep to myself) it doesn't belong there without references.

Steveicarus 14:40, 18 May 2007 (UTC)

I have been associated with all three major simulator vendors (Cadence, Mentor Graphics and Synopsys). And as of this note work for Synopsys. RickEversole (talk) 16:41, 19 February 2020 (UTC)

Disclosure

Sorry that I failed to disclose that. Yes, I'm the author of LogicSim. Being an expert in this area, I think I'm deemed appropriate as a person who creates this list as a draft. Anyone is free to modify whatever I write, as this is Wikipedia. I tried to provide an unbiased viewpoint from my point of view. This list was not meant to be used as marketing tool as claimed by Stephen, otherwise I wouldn't have listed other commercial and open-source simulators side-by-by unbiased. The creation of this list is necessary in order to provide an unbiased view point of Verilog simulators, as most blogs or websites found on the Internet will only provide their own preferences and views. Besides most Verilog simulator lists available on blogs or websites are usually incomplete or biased. So here goes the Wiki entry of its own. Hope this list will continue to grow and improve as time passes.

verilog expert

who ? Ngsayjoe ? You maybe an expert in your own implementation of Verilog/System verilog. The real test is in real world design. Everyone can claim being an expert. By the real experts in Verilog simulation are yet to claim they are one. Your should let your product do the talking. Let your simulator proves you right, So far, no luck.

Chonguantan --> from Mentor Graphics?

Chonguantan you seem to be talking on behalf of Mentor Graphics your employer?

=== chongguan tan sorry, somehow wiki keeps appending to this posting.

I can't speak for Mentor Graphics. I speak from my heart. As an ex-simultor R&D engineer and user, I know what is good and what is bad. I can only honestly classify Modelsim as "1 of the 3 dominating simulators".

I am no Verilog Expert, and don't pretend to be one.

It truelly sucks to see the simulators arranged alphabetically. "important" to the industry should be the main factor, and 'year entering market' should be the second. It really sucks to see Verilog-XL buried at the end of the list,

SystemVerilog & VCS

Having worked on the GUI used by Synopsys, I can understand how they were able to integrate SystemVerilog quite quickly. The VCS GUI was developed independently of the simulator, (by Simulation Technologies, later Summit Design )and was designed to be able to work with different simulators and different HD Languages (concurrently, no less). With SystemVerilog being just another simulator using just another language, developing the software wrapper to integrate the simulator into the VCS GUI wouldn't have been a monumental task. --64.238.49.65 (talk) 13:43, 25 March 2008 (UTC)

This is a list

>> It truelly sucks to see the simulators arranged alphabetically

This is a list of simulator vendors, henceforth it should be arranged by order of alphabetics, just like any other lists on Wikipedia.

Example, http://en.wikipedia.org/wiki/NASDAQ-100

If you write a review, then you may like to arrange it in whatever order you like.

Biased list

Somebody really needs to take out some of the "opinion" information. Come on here. A simulator is "maybe the best among the big 3" and another one is "getting its butt kicked real bad by the competitions?" Does somebody have facts to back up these opinions?

Also, it would seems to be accpetable to me to break the list up into "Dominant Players (big 3)," "Open Source," and "Others."

...

"Big 3", to me, means those simulators actively validated for ASIC tape-out signoff at major foundries. None of the smaller players have that level of qualifcation, so no (modern) ASIC design team would dare run gate-level simulations on anything other the big-3 simulators.

The FPGA-market has a different set of players, and focus more on suite-integration (state-diagram editor, automatic waveform generation for documentation/testbench automation, push-button launch of FPGA-synthesis engine, etc.)

ICarus not save

The Icarus source/exe aren t spyware free. So I think it shouldn t be shown here... —Preceding unsigned comment added by 91.3.78.137 (talk) 21:18, 29 September 2008 (UTC)

If true this should be noted (with references of course) but that is not a good reason to delete the entry. The list should be complete.

Zencuke (talk) 01:12, 7 March 2019 (UTC)

Axiom?

How about http://www.axiom-da.com/mpsim.html 66.127.55.23 (talk) 05:05, 7 January 2011 (UTC)

Generalize this to VHDL/Verilog simulators

This article should be renamed to "List of Verilog and VHDL" simulators. The two overlap, most simulators support both. I'm not sure how to rename an article in Wikipedia. —Preceding unsigned comment added by 174.116.190.217 (talk) 20:57, 16 January 2011 (UTC)

I think the current title is fine. It is clear and unambiguous. Plus why restrict it to Verilog and VHDL. Why not SystemVerilog? Why not SystemC. New languages may appear. The list should include simulators for any synthesizable HDL.

Zencuke (talk) 01:07, 7 March 2019 (UTC)

Title is fine. But "history" is not well written and the this article should cross reference Hardware description language which has extensive (though possibly incomplete) but unfortunately very technical descriptions of various HDL languages (primarly Verilog/SystemVerilog, VHDL and SystemC) RickEversole (talk) 15:14, 19 February 2020 (UTC)

Wrong list

The Tachyon Design seems to be open source, is it fair to include it in the second list? — Preceding unsigned comment added by 24.59.190.49 (talk) 21:27, 9 October 2015 (UTC)

Incomplete list

The list of commercial simulators does not mention SystemVision from Mentor Graphics, Simplorer from Ansys, or Saber from Synopsys. It does mention Mentor's Modelsim, which is integrated into SystemVision. SystemVision and Simplorer support VHDL-AMS. Saber supports VHDL-AMS and the proprietary MAST modeling language. These are all simulators I have used. — Preceding unsigned comment added by 68.191.34.123 (talk) 13:48, 27 March 2017 (UTC)

SystemC is missing from the "language" column

Even though these days it is mostly seen in verification SystemC is an ISO Standard HDL and synthesizable language. I know at least Cadence Stratus and Mentor Graphics Catapolt can systhesize it. There may be other companies that offer SystemC synthesizors but that is not really an issue here. I mention it mostly to prove it is an honest to golly HDL which should be listed here. There is even an Accelera Standard document which defines the "SystemC Synthesizable Subset."

You would have to ask Cadence and Mentor about their customers but unofficial word from a Cadence AFE I know suggests it is popular for developing ASICs needing complex math. It seems to also be a player in the "High Level Synthesis" world. C/C++ is already popular for complex algorith development, both for speed reasons and because more people know it. If the algorith is developed and tested in SystemC as C++ and then synthesized directly from the resulting SystemC that skips the notoriously high risk process of reimplementing it in a different HDL. There is no translate/reimplement step to add bugs.

Note: The Accellera version from the Accellera web page should be listed in the free simulator section and most commercial Verilog and VHDL simulators will also simulate SystemC for verification purposes. The commercial simulators I know about (big 3) that simulate SystemC are all based on the Accellera simulator code base as was the intent. My knowledge is limited though. I only know about Accellera and the 'big 3' SystemC simulators. But if no one else takes a stab at it I might give it a shot. SystemcC simulation is already mentioned in the 'description' column for two of the big-3. I would mostly 1) add an Accellera entry to the free list and 2) add SystemC 2.3.3 (current version) to the language column in the commercial list for the companies that I know about because everyone supports that version. I don't know about support for earlier versions so i wouldn't be able to add that. I might add a mention and link to the synthesizable subset document.

Zencuke (talk) 00:52, 7 March 2019 (UTC)

Why the inconsistancy between the free and commercial tables?

The free section has 2 tables broken out by language but the commercial sections lumps them all together into one table. I can see arguements for either format but it should be consistant.

Zencuke (talk) 00:52, 7 March 2019 (UTC)