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Ingenic Semiconductor

(Redirected from Media Extension Unit)

Ingenic Semiconductor is a Chinese fabless semiconductor company based in Beijing, China founded in 2005. They purchased licenses for the MIPS architecture instruction sets in 2009 and design CPU-microarchitectures based on them. They also design system on a chip products including their CPUs and licensed semiconductor intellectual property blocks from third parties, such as Vivante Corporation, commission the fabrication of integrated circuits at semiconductor fabrication plants and sell them.

Ingenic Semiconductor Co., Ltd.
Native name
君正集成电路股份有限公司
Ingenic Semiconductor
IndustryFabless semiconductors, Semiconductors, Integrated circuit design
Founded2005; 19 years ago (2005)
FounderLiu Qiang (刘强)
HeadquartersBeijing, China
Key people
Liu Qiang (Chairman)
ProductsCPUs (XBurst), SoCs (JZxxx)
Websitewww.ingenic.com.cn/en

XBurst microarchitecture

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Early XBurst CPU microarchitectures were based upon the MIPS32 revision 1 and newer models are based on the MIPS32 revision 2 instruction set. It implements an 8-stage pipeline XBurst CPU technology consists of 2 parts:

  • A RISC/SIMD/DSP hybrid instruction set architecture which enables the processor to have the capability of computation, signal processing and video processing. This includes the Media Extension Unit (MXU), a 32-bit SIMD extension. All JZ47xx series CPUs with Xburst uA support MXU, except for the JZ4730.[1][2]
  • MXU has its own register set, distinct from the general purpose MIPS registers. It consists of sixteen 32-bit data registers and a 32-bit control register.[3] CPUs which support MXU are used in MIPS Creator single-board computers. They are also present in various tablets, handheld game devices, and embedded devices.

XBurst2 microarchitecture

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XBurst2 development was, in summer 2013, expected to be completed by the first half of 2014.[4] However, XBurst2 was eventually introduced in 2020 in the X2000,[5] with the microarchitecture offering a dual-issue/dual-threaded CPU design based on MIPS32 Release 5.[6]

XBurst-based SoCs

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Ingenic JZ4725
 
Ingenic JZ4730
 
Ingenic JZ4740

SoCs incorporating the XBurst microarchitecture:[7]

Model Launch Fab (nm) XBurst version MIPS architecture version Core clock (MHz) L1 Dcache
[kB] 		L1 Icache
[kB] 		L2 cache
[kB] 		FPU GPU VPU Datasheet Package Notes
Jz4730 2006[8] 180 XBurst1 MIPS32 rev1 336 16 16 N/A N/A N/A N/A Jz4730 BGA256
Jz4740 2007[8][9] 180 XBurst1 MIPS32 rev1 + SIMD 360 Jz4740 BGA193 adds RMVB, MPEG-1/2/4 decoding capability up to D-1 resolution thanks to SIMD instruction set
Jz4720 2007[8][9] 180 XBurst1 240 Jz4720 COB186
Jz4725B 2009[10][11] 160 XBurst1 360 Jz4725 QFP128
Jz4750 2009[10][11] 180 XBurst1 MIPS32 rev1 + SIMD2 360 480p Jz4750 BGA256 adds TV encoder
Jz4755 2009 160 XBurst1 400 576P Jz4755 QFP176 second core is for video processing only
Jz4760 2010 130 XBurst1 528[12] yes Vivante GC200 720p JZ4760 BGA345 second core is for video processing only, IEEE754-complient FPU
600 JZ4760B
Jz4770 2011 65 XBurst1 MIPS32 rev2 + SIMD2 1000 256 yes Vivante GC860[13] 1080p JZ4770 BGA379 1080p video decoding unit for h.264, VC-1 and VP8 (a secondary 500 MHz MIPS processor with SIMD extension)
Jz4775[14] 65 XBurst1 MIPS32 rev2 + SIMD2 1000 32 32 256 yes X2D Core 720p JZ4775 BGA314 720p video decoding unit for h.264, VC-1 and VP8 (a secondary 500 MHz MIPS processor with SIMD extension)
Jz4780 2012 40 XBurst1 Dual MIPS32 rev2 + SIMD2 1200[15] 32 each 32 each 512 yes PowerVR SGX 540 1080p JZ4780 BGA390 Dual core (SMP) XBurst CPU, 1080p video decoding unit for h.264, VC-1 and VP8 (a secondary 500 MHz MIPS processor with SIMD extension)
x1000[16] 2015[17] 65 XBurst1 MIPS32 + SIMD 1000 16 16 128 yes x1000 Archived 2022-10-03 at the Wayback Machine BGA190 LPDDR 32/64MB, SLCD interface, Camera interface, Audio Codec up to 192 kHz
x2000 2020[18] 28 XBurst2 Dual MIPS32 + SIMD 1500 32 each 32 each 512 yes 1080p x2000 BGA270 LPDDR2/3 128/256MB

Adoption

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XBurst1-based SoCs are commonly used in tablet computers, portable media players, digital photo frames and GPS devices:

The JZ4730 CPU is used in the Skytone Alpha-400 and its variants.[19] The Jz4720 is utilized in the Copyleft Hardware project Ben NanoNote.[20] Another popular device, the Dingoo gaming handheld, uses the JZ4732, a de facto JZ4740. Game Gadget is using the JZ4750. Velocity Micro T103 Cruz and T301 Cruz 7-Inch Android 2.0 Tablets used JZ4760. The JZ4770 SoC is used in several of the Ainol Novo 7 Android tablets[21] and 3Q Tablet PC Qoo! IC0707A/4A40. JZ4770 SoC is also used in the dedicated handheld Neo Geo X[22] and open source handheld GCW Zero[23] running on OpenDingux.[24] The JZ4780 is used in ImgTec's MIPS based single-board computer (SBC); The Creator CI20[25]

Manufacturer Model(s) Type CPU Operating System
Qi Hardware Ben NanoNote Handheld Computer Ingenic JZ4720 OpenWRT (custom)
Skytone Skytone Alpha-400 Netbook Ingenic JZ4730 Linux
Dingoo Digital Dingoo Handheld Game Console Ingenic JZ4732 OpenDingux
Blaze Europe Game Gadget Handheld Game Console Ingenic JZ4750 unknown
Velocity Micro Cruz T103, T301 Tablet Ingenic JZ4760 Android 2.0
GCW GCW Zero Handheld Game Console Ingenic JZ4770 OpenDingux
unknown Neo Geo X Handheld Game Console Ingenic JZ4770 unknown
ImgTec Creator CI20 Single-board computer Ingenic JZ4780 Linux

See also

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References

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  1. ^ "JZ4780 Mobile Application Processor - Programming Manual" (PDF). Imagination Technologies. Archived from the original (PDF) on 4 March 2016. Retrieved 29 December 2015.
  2. ^ "Development:MXU". Dingoonity Wiki. Retrieved 29 December 2015.
  3. ^ "Ingenic SIMD/DSP Instruction Set" (PDF). Ingenic Semiconductor Co. Ltd. Retrieved 30 December 2015.[permanent dead link‍]
  4. ^ "XBurst2 SoC being developed". Archived from the original on 2013-10-14. Retrieved 2013-10-12.
  5. ^ "Ingenic added X2000 multi-core heterogeneous cross-border processor and halley5 development platform" (Press release). Retrieved 13 December 2020.
  6. ^ "Ingenic CPU Technologies". Ingenic Semiconductor. Retrieved 13 December 2020.
  7. ^ "Ingenic Xburst Products". Archived from the original on 2011-09-04.
  8. ^ a b c "Shǒucì gōngkāi fāxíng gǔpiào bìng zài chuàngyè bǎn shàngshì zhāogǔ shuōmíngshū" 首次公开发行股票并在创业板上市招股说明书 [Prospectus for Initial Public Offering and Listing on Growth Enterprise Markets Board] (PDF) (in Chinese). Ingenic Semiconductor Co. Ltd. 2011-05-19. Retrieved 2023-09-24.
  9. ^ a b "Application Processor". Ingenic Semiconductor Co. Ltd. Archived from the original on 2008-02-09. Retrieved 2008-02-09.
  10. ^ a b "Application Processor". Ingenic Semiconductor Co. Ltd. Archived from the original on 2008-12-26. Retrieved 2008-12-26.
  11. ^ a b "处理器产品". Ingenic Semiconductor Co. Ltd. Archived from the original on 2009-03-23. Retrieved 2009-03-23.
  12. ^ "JZ4760B 32 Bits Microprocessor - Application Notes 01" (PDF). Ingenic Semiconductor Co. Ltd. Retrieved 2023-10-05.
  13. ^ "::: Vivante Corporation I News :::". Archived from the original on 2012-06-03. Retrieved 2011-12-13.
  14. ^ Suspected to be called as JZ4774 sometime
  15. ^ JZ4780 Mobile Application Processor Data Sheet[permanent dead link‍]
  16. ^ "Ingenic Semiconductor_M200 M150 JZ4780 JZ4775 JZ4760B". www.ingenic.com.cn. Retrieved 2020-06-02.
  17. ^ Williams, Alun (2015-10-07). "1GHz MIPS chip aimed at human-machine interfacing". Electronics Weekly. Retrieved 2020-06-02.
  18. ^ "1GHz MIPS chip aimed at human-machine interfacing". 2020-07-12. Retrieved 2020-07-13.
  19. ^ Hachman, Mark (May 30, 2008). "Mystery Chip Powers New $299 UMPC - News and Analysis by PC Magazine". 080707 pcmag.com
  20. ^ Ben NanoNote Hardware Components
  21. ^ "$79 Ainol Novo 7 Paladin Tablet Does Ice Cream Sandwich". Archived from the original on 2012-01-17. Retrieved 2012-01-23.
  22. ^ "Neo-Geo X official site". Archived from the original on 2012-08-17. Retrieved 2013-01-10.
  23. ^ "GCW-Zero official site".
  24. ^ http://www.mips.com/news-events/newsroom/newsindex/index.dot?id=71045 Archived 2013-08-16 at the Wayback Machine Lowest-Cost Android 4.1 Tablet in 2012 is based in MIPS
  25. ^ "Tom's Hardware CI20". 19 December 2014.
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